Charge retention is an important characteristic of reliable non-volatile memory devices. The oxide surrounding the polysilicon of the floating gate device of a non-volatile memory cell serves as an insulator for preventing charge loss. Damage to oxide surrounding the polysilicon of floating gate devices has been associated with charge loss in non-volatile memory devices. Damage to the oxide may result, for example, from the actual doping of the oxide and/or from an increased chemical doping level of the polysilicon next to the oxide.
In the past, the application of a hard mask oxide was used to minimize damage to the oxide surrounding floating gate devices. The hard mask minimized damage on the oxide by isolating both the oxide and the polysilicon from doping processes such as those used for source drain implantation. Current salicide processes, however, utilize a layering process which involve application of a metal, such as titanium, over the polysilicon in order to lower the resistive properties of the polysilicon. This process prevents the application of the hard mask.
Thus, what is needed is a method and apparatus for addressing the problem of oxide damage along the polysilicon gate.